By Rajesh Garg
This booklet is inspired by way of the demanding situations confronted in designing trustworthy integratedsystems utilizing smooth VLSI tactics. The trustworthy operation of built-in Circuits (ICs) has develop into more and more tough to accomplish within the deep sub-micron (DSM) period. With consistently lowering machine function sizes, mixed with decrease offer voltages and better working frequencies, the noise immunity of VLSI circuits is lowering alarmingly. therefore, VLSI circuits have gotten extra prone to noise results comparable to crosstalk, strength offer adaptations and radiation-induced tender errors.
This e-book describes the layout of resilient VLSI circuits. It provides algorithms to investigate the hazardous results of radiation particle moves and processing adaptations at the electric habit of VLSI circuits, in addition to circuit layout suggestions to mitigate the influence of those problems.
- Describes the state-of-the-art within the parts of radiation tolerant circuit layout and method edition tolerant circuit design;
- Presents analytical techniques to check successfully the severity of electric results of radiation/process diversifications, in addition to thoughts to lessen the consequences because of those problems;
- Distills content material orientated towards nuclear engineers into modern algorithms and strategies that may be understood simply and utilized by way of VLSI designers.
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Extra info for Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
1) will lead to an inaccurate analysis. Through experiments it was found that ignoring “ results in an under-estimation of the pulse width of the radiation-induced voltage glitch by 10%. 1) effectively diminishes the severity of the radiation particle strike, and hence leads to an optimistic estimate for the voltage glitch. Thus, it is important to consider “ for an accurate analysis. The model presented in this chapter considers the contribution of “ . In the remainder of this chapter, Sect. 2 briefly discusses related previous work on modeling radiation-induced transients in combinational circuits.
E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583– 602, 2003. 12. Q. Zhou and K. Mohanram, “Gate sizing to radiation harden combinational logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155–166, Jan. 2006. 13. D. Binder, C. Smith, and A. Holman, “Satellite anomalities from galactic cosmic rays,” IEEE Transactions on Nuclear Science, vol.
On the other hand, if a gate is less susceptible to radiation events, then pulse width of the voltage glitch will be lower. Hence, the pulse width of the radiation-induced voltage glitch is often used as the radiation robustness metric of choice. 1). Both these factors improve the accuracy of the analytical model for the pulse width computation. The proposed model is applicable to any logic gate, with arbitrary gate size and loading, with different amounts of charge collected due to the radiation strike.